The present invention relates to integrated circuit structures and fabrication methods and more specifically to improving conductance on silicided polysilicon gate lines.
Even as the size of integrated circuits shrink, the demand for higher performance, including decreased resistance on conductive lines, increases. In logic integrated circuits, polysilicon gate lines commonly use a self-aligned silicide ("salicide") to reduce gate resistance and gate propagation delay. As device sizes shrink, smaller gate sizes mean that there are fewer nucleation centers for the transformation of titanium disilicide from a high resistance state (C49) to a low resistance state (C54), giving less desirable results. Further background in silicided gate structures can be found in Silicon Processing for the VLSI Era, Wolf et al., 1986 (see especially Volume 1, Chapter 11 on "Refractory Metals and Their Silicides in VLSI Fabrication" and Volume 2, Chapter 3 on "Contact Technology and Local Interconnects for VLSI"), which is hereby incorporated by reference.
Innovative Structures and Methods
Co-pending application Ser. No. 09/060,893, (Attorney Docket No. TI-21888), filed Apr. 15, 1998, and which is hereby incorporated by reference, discloses a method wherein the sidewall spacers adjacent a polysilicon gate are created to be lower in height than the gate, to expose at least 30 percent of the sidewall. This is followed by deposition of a metal, by a method which gives at least 50 percent step coverage, and heating to react the metal with exposed polysilicon to form a silicide. Since more of the gate is covered with silicide, the gate sheet resistance is lowered.
As is mentioned in the co-pending application, a further improvement to this silicidation process can be achieved by forming a silicide on the gate sidewalls which is thicker than the silicide on top of the gate. This is achieved by using an anisotropic metal etch after metal deposition, to thin the metal on horizontal surfaces, but not on the gate sidewall. This allows thin silicide formation on source and drain, with low silicon consumption, making it compatible with shallow junctions, and achieves low sheet resistance on the gates by thick silicide formation on the gate side walls.
Advantages of the disclosed method include:
lower sheet resistance on the gate; PA1 thickness of silicide can be reduced over source/drain regions to protect shallow junctions; PA1 silicide thickness is greater on sides of the gate, where it contributes to the desired low sheet resistance without causing the problems associated with thick suicides on source/drain regions; PA1 process is highly manufacturable, easy to implement.